Pulse Semiconductor Designing Battery-backed MEMORY using high speed SRAM

Saturday, 7 November 2015

The structure of a traditional embedded system has not modified for several decades. Figure one shows the block level diagram of a typical embedded system. A microcontroller or microchip is at the center of the system. relying upon the applying, system designers add or take away interfaces and peripherals as required. If the interior memory of the controller isn't ample, external reminiscences like Flash, SRAM and DRAMs ar used. Typically, Flash holds the code that's dead by the controller whereas SRAMs ar accustomed store runtime temporary variables and retain essential blocks of application knowledge. Power budget and performance have forever been 2 of the shaping criteria for choice of system parts, be it the controller or any peripherals. If performance is essential, designers tend to pick out the quickest parts, commercialism off for the next power budget. Similarly, if power is that the most significant criteria— like in a very battery-backed system—then designers tend to pick out parts with the smallest amount power consumption. As a result, embedded systems ar typically classified into 3 categories:
1. forever “ON” Systems: These systems guarantee that they're going to forever be power-driven from Associate in Nursing uninterrupted power supply. These ar high performance systems designed to control at the best frequency of operation.
 2.Battery-powered Systems: Associate in Nursing on-board battery is that the solely supply of power for these systems (i.e. a mobile phone). whereas performance is a crucial criteria for such systems, having longer battery life first-rate the priority list. thus these systems ar designed with parts that consume the bottom power.
3.Battery-backed Systems: These systems should be able to operate dependably even though they lose their aboard power offer. To avoid the loss of essential knowledge throughout these power failures, system designers offer atiny low battery (typically a 240mAh coin battery) to produce make a copy for essential functions like SRAM retention and maintaining the period clock (RTC). A battery-backed system operates on the out there power offer throughout traditional operational conditions. betting on the memory mapping, it will execute code from Flash then store ends up in SRAM. It becomes essential to store this knowledge even throughout power failures. Figure 1. diagram of a typical embedded system
Figure 2. Power consumption pattern of a battery-backed system to handle this issue, the SRAM is connected to Associate in Nursing alternate on board battery. throughout traditional operation, the on-board offer powers the system, and through equipment failure, a supervisor chip can switch the SRAM offer to the aboard battery and place the SRAM in its standby mode of operation. sit down with “Design Recommendation for Battery-Backed SRAMs” for additional details on specific battery-backed system implementation techniques.

Figure two shows the everyday power usage of SRAM in a very battery-backed system. The supervisor routes the board power offer throughout traditional modes of operation. On equipment failure, the SRAM is switched to the on-board battery and is disabled by the supervisor chip. The system will stay during this mode for as long because the battery lasts. Once board power offer resumes, the supervisor chip can bit by bit resume powering the SRAM


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