Showing posts with label VLSI-Very Large Scale Integration. Show all posts
Showing posts with label VLSI-Very Large Scale Integration. Show all posts

VLSI-Digital Design Techniques Top-Down Design vs. Bottom-Up Design

Wednesday, 21 August 2013

Digital Design Techniques Top-Down Design vs. Bottom-Up Design

Digital circuits can be designed at Top-Down or from Bottom-Up. In bottom-up design,
the details are figured out first. For example, transistor or mask-level cells are designed
first. Later the individual cells are connected to form the complete design.

In top-down design, the system is designed at an abstract level such as at behavioral or
architectural level first, details are figured out later. For example, the top-level block
diagram with system input and output is designed first. Then RT level description is
written. Gate-Level Description is generated later. Afterwards, it is converted to Mapped

Layout to prepare for FPLD Programming or Mask-Level Layout is generated for
sending design to Fabrication (for fabrication of an ASIC).

Top-Down design takes away from Logic (Gate) and Circuit (Transistor) to abstract
behavior, macro architecture and abstract programming (HDL)

VLSI-Digital VLSI Circuit Design

Digital VLSI Circuit Design

Fundamentals
  • Logic Styles (NMOS, CMOS, Bipolar, Pseudo-NMOS, Dynamic CMOS, Transmission
Gate, Pass Transistor logic etc.)
Implementation Technologies (Full-Custom design and Semi-Custom design including
  • ASIC (MPGA and SBIC), FPLD (CPLD and FPGA) etc.)
  • Boolean Logic
  • Logic Minimization
 Practical Aspects
  • Combinational Logic Design: Adders, Multipliers, Multiplexers, ALUs etc.
  • Sequential Logic Design: Registers, Register Files, Counters, Shift Registers, Finite State
          Machines (FSM) etc.
  • Memory Design: RAM (SRAM, DRAM), ROM (PROM. EPROM, EEPROM, Flash) etc.
  • Electronic Design Automation (EDA), Computer Aided Design (CAD), Computer Aided
  • Engineering (CAE) tools
  • System-level, Architecture-level, Register Transfer (RT) Level design.  
  • High-Level or Behavioral Synthesis/Architecture Description Language (ADL/)Systemon-
    Chip (SOC) Design/Analog and Mixed-Signal (Digital + Analog) Design .
  • Computer Architecture (Architecture Level)
  • VHDL (or Verilog) Modeling and Synthesis (RT-Level)
  • Microprocessor (System-Level)
  • Clock Generators and Clock Buffers
  • Clock Synchronizers, Clock Managers, Clock Tree Insertion
  • Test Synthesis, Fault Analysis, Scan-chain
  • Speed (Delay)
  • Power Consumption
  • Cost
  • Reliability
  • Logic-Level (Gate-Level), Circuit-Level (Transistor-Level) and Physical Design
    (Mask/Silicon-Level) Design/Layout Synthesis

VLSI-Very Large Scale Integration

VLSI-Very Large Scale Integration

1.VLSI Design or VLSI Circuit Design refers to
designing high-density electronic circuits, typically
circuits that contain transistor in excess of 100,000.
2.There are 2 types of VLSI Circuits-Analogue and
Digital.
3.VLSI Circuit Design typically (and in this class)
involves discussions about different logic styles and
implementation technologies for implementing
digital circuits, transistor and mask-level layout and
interconnect, fabrication technologies and analysis of
various design and performance parameters such as
Speed, Power, Cost, Reliability etc.
4.The discussion typically is at Logic (Gate), Circuit
(Transistor) and Physical/Mask (Silicon) Level.
5.Integration simply means more devices per chip.
Integration improves design, that is its speed, power
consumptions, size—and reduces manufacturing
costs.

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