EDA Tools:VLSI

Sunday, 25 August 2013

EDA Tools:VLSI

Electronic Design Automation (EDA):
EDA tools are specific Computer Aided Design (CAD) and Computer Aided Engineering
(CAE) tools that are used to verify and implement digital circuits originally defined
through an HDL.

Key Processes:

1. Synthesis:
An automated process that takes in a Register Transfer (RT) level design description—
described at a Hardware Description Language (HDL)—converts it to a generic Gate-
Level structural description, optimizes it for Speed or Area or other design constraints
and customizes the description for a specific target technology (FPLD/ASIC) using
technology cells available in that target technology.

2. Cell Placement and Floorplanning:
For MPGAs:
Cell placement process customizes the cells of an MPGA-type ASIC with appropriate
metal connections to form gates and flip-flops (a generic 6 or 4-transistor cell becomes a
4-transistor 2-input NAND gate), and arranges the cells on the die.
For CBICs:
Cell placement process places the constant-height, variable-width standard cells, which
are already pre-defined and layout-ready and are arrayed in rows and columns in
Standard Cell-based ASICs (CBIC).
Automated or manual Floorplanning is required to intelligently places cells in specific
segments/areas of the chip.
For FPLDs:
Cell placement selects gates of which function blocks in CPLDs or which LUTs in
FPGAs will be connected.
Floorplanning:
Automated or manual Floorplanning is required to intelligently place cells in specific
segments/areas of the chip.

3. Design for Test (DFT) Insertion and Automatic Test Pattern Generation (ATPG)
Special test circuits are embedded in the chip that enables a tester to use a few external
pins to test the entire internal circuit. Test patterns are generated before the device is
fabricated that will check whether a set of test vectors will detect a set of faults. This step
is designed to test for process-induced faults not design errors.

4. Clock-Tree Insertion
Clock Tree Insertion involves selecting the clock distribution strategy for the chip and
implementing that strategy. One has to ensure that all segments of the chip receive the
system clock at the same time. This is essential for high-speed designs. To minimize
clock skew, it is generally required to route the clock and clock buffers before the main
logic placement and routing is done.

5. Cell Routing
Routing process connects the cells of MPGAs, CBICs, CPLDs or FPGAs to complete the
layout. Routing is divided into 2 steps: global routing and detailed routing. Global routers
initially attempt to connect individual cells to global routing network of the chip. Later
detailed routers places the actual geometry needed to complete signal connections. In
some cases routers can also route over top of the cells.

Logical effort

Logical effort

Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an
inverter delivering the same output current.
Logical Effort indicates how much worse a gate is at producing output current as
compared to an inverter.
Cin can be calculated by estimating how much gate-width each input is seeing.
Logical Effort G = Cin/ Cref
Cref is the input capacitance of a symmetrical inverter, where fall-time = rise-time. This
was realized by increasing PMOS gate width to twice the gate width of the NMOS.
So, input of this inverter will see 3 gate-widths (2 for PMOS and 1 for NMOS).
A symmetrical inverter sees 3 gate-widths in its input. So, Logical Effort for this inverter
G = Cin/Cref = 3C/3C = 1

VLSI-Digital Design Techniques Top-Down Design vs. Bottom-Up Design

Wednesday, 21 August 2013

Digital Design Techniques Top-Down Design vs. Bottom-Up Design

Digital circuits can be designed at Top-Down or from Bottom-Up. In bottom-up design,
the details are figured out first. For example, transistor or mask-level cells are designed
first. Later the individual cells are connected to form the complete design.

In top-down design, the system is designed at an abstract level such as at behavioral or
architectural level first, details are figured out later. For example, the top-level block
diagram with system input and output is designed first. Then RT level description is
written. Gate-Level Description is generated later. Afterwards, it is converted to Mapped

Layout to prepare for FPLD Programming or Mask-Level Layout is generated for
sending design to Fabrication (for fabrication of an ASIC).

Top-Down design takes away from Logic (Gate) and Circuit (Transistor) to abstract
behavior, macro architecture and abstract programming (HDL)

VLSI-Digital VLSI Circuit Design

Digital VLSI Circuit Design

Fundamentals
  • Logic Styles (NMOS, CMOS, Bipolar, Pseudo-NMOS, Dynamic CMOS, Transmission
Gate, Pass Transistor logic etc.)
Implementation Technologies (Full-Custom design and Semi-Custom design including
  • ASIC (MPGA and SBIC), FPLD (CPLD and FPGA) etc.)
  • Boolean Logic
  • Logic Minimization
 Practical Aspects
  • Combinational Logic Design: Adders, Multipliers, Multiplexers, ALUs etc.
  • Sequential Logic Design: Registers, Register Files, Counters, Shift Registers, Finite State
          Machines (FSM) etc.
  • Memory Design: RAM (SRAM, DRAM), ROM (PROM. EPROM, EEPROM, Flash) etc.
  • Electronic Design Automation (EDA), Computer Aided Design (CAD), Computer Aided
  • Engineering (CAE) tools
  • System-level, Architecture-level, Register Transfer (RT) Level design.  
  • High-Level or Behavioral Synthesis/Architecture Description Language (ADL/)Systemon-
    Chip (SOC) Design/Analog and Mixed-Signal (Digital + Analog) Design .
  • Computer Architecture (Architecture Level)
  • VHDL (or Verilog) Modeling and Synthesis (RT-Level)
  • Microprocessor (System-Level)
  • Clock Generators and Clock Buffers
  • Clock Synchronizers, Clock Managers, Clock Tree Insertion
  • Test Synthesis, Fault Analysis, Scan-chain
  • Speed (Delay)
  • Power Consumption
  • Cost
  • Reliability
  • Logic-Level (Gate-Level), Circuit-Level (Transistor-Level) and Physical Design
    (Mask/Silicon-Level) Design/Layout Synthesis

VLSI-Very Large Scale Integration

VLSI-Very Large Scale Integration

1.VLSI Design or VLSI Circuit Design refers to
designing high-density electronic circuits, typically
circuits that contain transistor in excess of 100,000.
2.There are 2 types of VLSI Circuits-Analogue and
Digital.
3.VLSI Circuit Design typically (and in this class)
involves discussions about different logic styles and
implementation technologies for implementing
digital circuits, transistor and mask-level layout and
interconnect, fabrication technologies and analysis of
various design and performance parameters such as
Speed, Power, Cost, Reliability etc.
4.The discussion typically is at Logic (Gate), Circuit
(Transistor) and Physical/Mask (Silicon) Level.
5.Integration simply means more devices per chip.
Integration improves design, that is its speed, power
consumptions, size—and reduces manufacturing
costs.

The Global System for Mobile (GSM)

Tuesday, 20 August 2013



GSM uses both TDMA and Frequency Division Multiple Access (FDMA) to transmit and recover information as shown in Figure 1. These systems use data packets at specific times at specific frequencies. Thus, several conversations take place simultaneously and at the same frequency using different time slots. Systems are also frequency duplex so that the transmitting and receiving frequencies are different, and both sides of the transmission (Mobile-to-Base and Base-to-Mobile) are concurrent.  The characteristics of GSM system are shown in Table 1. The spacing between the carriers in GSM system is 200 kHz. Eight time slots carry speech and data in a GSM system.  The bandwidth for the GSM system is 25 MHz, which provides 125 carriers each having a bandwidth of 200 kHz. Due to interference to other systems, the very first carrier is not used, thus reducing the number of carriers to 124.  With eight users per channel there are about 1,000 actual speech or data channels. The number of channels will double to about 2,000 as the half rate speech coder is introduced. The frequency band used for the uplink is 890 MHz to 915 MHz (from MS to base station) and for the downlink 935 MHz to 960 MHz (from base station to MS).


The modulation method in GSM is Gaussian Minimum Shift Keying (GMSK), which facilitates the use of narrow bandwidth and coherent detection capability. In GMSK the rectangular pulses are passed through a Gaussian filter prior to their passing through a modulator. This modulation scheme almost satisfies the adjacent channel power spectrum density requirement of -60 dBc specified by CCIR. The normalized pre-Gaussian bandwidth is kept at 0.3, which corresponds to a filter bandwidth of 81.25 kHz for an aggregate data rate of 270.8 Kbps. With 200 kHz of carrier spacing and this data rate, the spectral efficiency of the system is 1.35 b/s/Hz. With the bit interval of 3.7 ms, the GSM signal will encounter significant intersymbol interference in the mobile radio path due to multipath ( multipath minimal delay spread 3 ms to 6 ms in urban areas). As a consequence, an adaptive equalizer is used. There are eight time slots in a frame and 26 or 51 frames in a multiframe. With 270.8 Kbps divided among eight users in GSM, the per user data rate is 33.85 Kbps. The speech coder is a regular pulse excitation with long-term predictor (RPE-LTP) for a full rate speech that converts speech to 13 Kbps.  There are five different categories of mobile telephone units specified for the European GSM system: 0.8W, 2W, 5W, 8W, and 20W. The power level can be adjusted to vary between 3.7 mW to 20W. To optimize co-channel interference, each BS individually directs MS to use the minimum power setting that is necessary for reliable transmission. The setting is determined by BS and provided to the MS. The GSM air interface allows for frequencies to be hopped to prevent multipath problems resulting in excessive bit error rates. Both the mobile and the base station will use Discontinuous Transmission (DTx). This will allow the mobile to save the battery life and the base station to reduce co-channel interference.

Why GSM-Global System for Mobile

Thursday, 8 August 2013



Why GSM

The GSM study group aimed to provide the followings through the GSM:
*       ·          Improved spectrum efficiency.
*       ·          International roaming.
*       ·          Low-cost mobile sets and base stations (BSs)
*       ·          High-quality speech
*       ·          Compatibility with Integrated Services Digital Network (ISDN) and other
            telephone company services.
*       ·          Support for new services.

What is GSM-Global System for Mobile Communication



What is GSM

If you are in Europe, Asia or Japan and using a mobile phone then most probably you must be using GSM technology in your mobile phone.
       #GSM stands for Global System for Mobile Communication and is an open digital  cellular technology used for transmitting mobile voice and data services. 
       #The GSM emerged from the idea of cell-based mobile radio systems at Bell Laboratories in the early  1970s. 
       #  The GSM is the name of a standardization group established in 1982 to create a common European        mobile  telephone standard.
#The GSM standard is the most widely accepted standard and is implemented globally.  
#The GSM is a circuit-switched system that divides each 200kHz channel into eight 25kHz time-slots.GSM operates in the 900MHz and 1.8GHz bands in Europe and the 1.9GHz and 850MHz bands in the US
#The GSM is owning a market share of more than 70 percent of the world's digital   cellular subscribers.
#The GSM makes use of narrowband Time Division Multiple Access (TDMA)  technique for transmitting signals.
#The GSM was developed using digital technology. It has an ability to carry 64  kbps to 120 Mbps of data rates.
# Presently GSM support more than one billion mobile subscribers in more than 210 countries throughout of the world.
      #The GSM provides basic to advanced voice and data services including Roaming service. Roaming is
      the ability to use your GSM phone number in another GSM network.

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