EDA Tools:VLSI
Electronic Design Automation (EDA):
EDA tools are specific Computer Aided Design (CAD) and Computer Aided Engineering
(CAE) tools that are used to verify and implement digital circuits originally defined
through an HDL.
Key Processes:
1. Synthesis:
An automated process that takes in a Register Transfer (RT) level design description—
described at a Hardware Description Language (HDL)—converts it to a generic Gate-
Level structural description, optimizes it for Speed or Area or other design constraints
and customizes the description for a specific target technology (FPLD/ASIC) using
technology cells available in that target technology.
2. Cell Placement and Floorplanning:
For MPGAs:
Cell placement process customizes the cells of an MPGA-type ASIC with appropriate
metal connections to form gates and flip-flops (a generic 6 or 4-transistor cell becomes a
4-transistor 2-input NAND gate), and arranges the cells on the die.
For CBICs:
Cell placement process places the constant-height, variable-width standard cells, which
are already pre-defined and layout-ready and are arrayed in rows and columns in
Standard Cell-based ASICs (CBIC).
Automated or manual Floorplanning is required to intelligently places cells in specific
segments/areas of the chip.
For FPLDs:
Cell placement selects gates of which function blocks in CPLDs or which LUTs in
FPGAs will be connected.
Floorplanning:
Automated or manual Floorplanning is required to intelligently place cells in specific
segments/areas of the chip.
3. Design for Test (DFT) Insertion and Automatic Test Pattern Generation (ATPG)
Special test circuits are embedded in the chip that enables a tester to use a few external
pins to test the entire internal circuit. Test patterns are generated before the device is
fabricated that will check whether a set of test vectors will detect a set of faults. This step
is designed to test for process-induced faults not design errors.
4. Clock-Tree Insertion
Clock Tree Insertion involves selecting the clock distribution strategy for the chip and
implementing that strategy. One has to ensure that all segments of the chip receive the
system clock at the same time. This is essential for high-speed designs. To minimize
clock skew, it is generally required to route the clock and clock buffers before the main
logic placement and routing is done.
5. Cell Routing
Routing process connects the cells of MPGAs, CBICs, CPLDs or FPGAs to complete the
layout. Routing is divided into 2 steps: global routing and detailed routing. Global routers
initially attempt to connect individual cells to global routing network of the chip. Later
detailed routers places the actual geometry needed to complete signal connections. In
some cases routers can also route over top of the cells.
Electronic Design Automation (EDA):
EDA tools are specific Computer Aided Design (CAD) and Computer Aided Engineering
(CAE) tools that are used to verify and implement digital circuits originally defined
through an HDL.
Key Processes:
1. Synthesis:
An automated process that takes in a Register Transfer (RT) level design description—
described at a Hardware Description Language (HDL)—converts it to a generic Gate-
Level structural description, optimizes it for Speed or Area or other design constraints
and customizes the description for a specific target technology (FPLD/ASIC) using
technology cells available in that target technology.
2. Cell Placement and Floorplanning:
For MPGAs:
Cell placement process customizes the cells of an MPGA-type ASIC with appropriate
metal connections to form gates and flip-flops (a generic 6 or 4-transistor cell becomes a
4-transistor 2-input NAND gate), and arranges the cells on the die.
For CBICs:
Cell placement process places the constant-height, variable-width standard cells, which
are already pre-defined and layout-ready and are arrayed in rows and columns in
Standard Cell-based ASICs (CBIC).
Automated or manual Floorplanning is required to intelligently places cells in specific
segments/areas of the chip.
For FPLDs:
Cell placement selects gates of which function blocks in CPLDs or which LUTs in
FPGAs will be connected.
Floorplanning:
Automated or manual Floorplanning is required to intelligently place cells in specific
segments/areas of the chip.
3. Design for Test (DFT) Insertion and Automatic Test Pattern Generation (ATPG)
Special test circuits are embedded in the chip that enables a tester to use a few external
pins to test the entire internal circuit. Test patterns are generated before the device is
fabricated that will check whether a set of test vectors will detect a set of faults. This step
is designed to test for process-induced faults not design errors.
4. Clock-Tree Insertion
Clock Tree Insertion involves selecting the clock distribution strategy for the chip and
implementing that strategy. One has to ensure that all segments of the chip receive the
system clock at the same time. This is essential for high-speed designs. To minimize
clock skew, it is generally required to route the clock and clock buffers before the main
logic placement and routing is done.
5. Cell Routing
Routing process connects the cells of MPGAs, CBICs, CPLDs or FPGAs to complete the
layout. Routing is divided into 2 steps: global routing and detailed routing. Global routers
initially attempt to connect individual cells to global routing network of the chip. Later
detailed routers places the actual geometry needed to complete signal connections. In
some cases routers can also route over top of the cells.
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