The CMOS inverter

 The CMOS inverter

Consider the circuit of the CMOS inverter below. When the input is high the pull-down
device (Mpd) is ON but Vgs of the p-channel device is zero and hence the pull-up device
(Mpu) is OFF such that the output pulls all the way to ground. When the input is low,
Vgs of the p-channel device is Vdd and hence it is ON. The pull-down device is OFF and
the output rises to Vdd.

Schematic of CMOS Inverter:

1. Logic-Level (Logic-Level refers to Gate-Level):

 

 2. Switch-Level (Switch-level refers to simplified Transistor-level):

 

3. Circuit-Level (Circuit-Level refers to Transistor-level):

Introduction to Circuit Simulation Using SPICE--CMOS Inverter

Introduction:

SPICE (Simulation Program with Integrated Circuit Emphasis) is a very powerful and
one of the most widely used simulator for electrical and electronic circuits at transistorlevel
(circuit-level in VLSI terms), especially for analogue and mixed-signal circuits.

This experiment aims at introducing you to some of the capabilities of the spice program
applied to CMOS VLSI circuit design. It can perform nonlinear dc, nonlinear transient,
linear ac analysis and other type of simulations. The circuit may contain resistances,
capacitors, inductors, mutual inductors, independent voltage and current sources, four
types of dependent sources, transmission lines, and four most common semiconductor
devices: diodes, BJTs, JFETs and MOSFETs. This experiment will use SPICE’s dc and
transient analysis capabilities to analyze circuits based on CMOS n-type and p-type
enhancement mode MOSFETs and illustrate the importance of such a simulator in VLSI
Design.

EDA Tools:VLSI

EDA Tools:VLSI

Electronic Design Automation (EDA):
EDA tools are specific Computer Aided Design (CAD) and Computer Aided Engineering
(CAE) tools that are used to verify and implement digital circuits originally defined
through an HDL.

Key Processes:

1. Synthesis:
An automated process that takes in a Register Transfer (RT) level design description—
described at a Hardware Description Language (HDL)—converts it to a generic Gate-
Level structural description, optimizes it for Speed or Area or other design constraints
and customizes the description for a specific target technology (FPLD/ASIC) using
technology cells available in that target technology.

2. Cell Placement and Floorplanning:
For MPGAs:
Cell placement process customizes the cells of an MPGA-type ASIC with appropriate
metal connections to form gates and flip-flops (a generic 6 or 4-transistor cell becomes a
4-transistor 2-input NAND gate), and arranges the cells on the die.
For CBICs:
Cell placement process places the constant-height, variable-width standard cells, which
are already pre-defined and layout-ready and are arrayed in rows and columns in
Standard Cell-based ASICs (CBIC).
Automated or manual Floorplanning is required to intelligently places cells in specific
segments/areas of the chip.
For FPLDs:
Cell placement selects gates of which function blocks in CPLDs or which LUTs in
FPGAs will be connected.
Floorplanning:
Automated or manual Floorplanning is required to intelligently place cells in specific
segments/areas of the chip.

3. Design for Test (DFT) Insertion and Automatic Test Pattern Generation (ATPG)
Special test circuits are embedded in the chip that enables a tester to use a few external
pins to test the entire internal circuit. Test patterns are generated before the device is
fabricated that will check whether a set of test vectors will detect a set of faults. This step
is designed to test for process-induced faults not design errors.

4. Clock-Tree Insertion
Clock Tree Insertion involves selecting the clock distribution strategy for the chip and
implementing that strategy. One has to ensure that all segments of the chip receive the
system clock at the same time. This is essential for high-speed designs. To minimize
clock skew, it is generally required to route the clock and clock buffers before the main
logic placement and routing is done.

5. Cell Routing
Routing process connects the cells of MPGAs, CBICs, CPLDs or FPGAs to complete the
layout. Routing is divided into 2 steps: global routing and detailed routing. Global routers
initially attempt to connect individual cells to global routing network of the chip. Later
detailed routers places the actual geometry needed to complete signal connections. In
some cases routers can also route over top of the cells.

Logical effort

Logical effort

Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an
inverter delivering the same output current.
Logical Effort indicates how much worse a gate is at producing output current as
compared to an inverter.
Cin can be calculated by estimating how much gate-width each input is seeing.
Logical Effort G = Cin/ Cref
Cref is the input capacitance of a symmetrical inverter, where fall-time = rise-time. This
was realized by increasing PMOS gate width to twice the gate width of the NMOS.
So, input of this inverter will see 3 gate-widths (2 for PMOS and 1 for NMOS).
A symmetrical inverter sees 3 gate-widths in its input. So, Logical Effort for this inverter
G = Cin/Cref = 3C/3C = 1

VLSI-Digital Design Techniques Top-Down Design vs. Bottom-Up Design

Digital Design Techniques Top-Down Design vs. Bottom-Up Design

Digital circuits can be designed at Top-Down or from Bottom-Up. In bottom-up design,
the details are figured out first. For example, transistor or mask-level cells are designed
first. Later the individual cells are connected to form the complete design.

In top-down design, the system is designed at an abstract level such as at behavioral or
architectural level first, details are figured out later. For example, the top-level block
diagram with system input and output is designed first. Then RT level description is
written. Gate-Level Description is generated later. Afterwards, it is converted to Mapped

Layout to prepare for FPLD Programming or Mask-Level Layout is generated for
sending design to Fabrication (for fabrication of an ASIC).

Top-Down design takes away from Logic (Gate) and Circuit (Transistor) to abstract
behavior, macro architecture and abstract programming (HDL)