The CMOS inverter

Sunday, 1 September 2013

 The CMOS inverter

Consider the circuit of the CMOS inverter below. When the input is high the pull-down
device (Mpd) is ON but Vgs of the p-channel device is zero and hence the pull-up device
(Mpu) is OFF such that the output pulls all the way to ground. When the input is low,
Vgs of the p-channel device is Vdd and hence it is ON. The pull-down device is OFF and
the output rises to Vdd.

Schematic of CMOS Inverter:

1. Logic-Level (Logic-Level refers to Gate-Level):
 2. Switch-Level (Switch-level refers to simplified Transistor-level):

3. Circuit-Level (Circuit-Level refers to Transistor-level):



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